The present invention relates to a semiconductor wafer manufacturing method and a semiconductor wafer manufactured using this method.
Semiconductor wafers, particularly silicon wafers for forming semiconductor devices are manufactured using the CZ (Czochralski) method or the magnetic field applied CZ method (MCZ method). Crystals grown using these methods contain octahedral void defects (Grown-in defects) from 0.1 to 0.3 .mu.m in void size at a volume density of about 10.sup.6 cm.sup.-3. Such defects seldom disappear using normal annealing. Accordingly, when LSIs or ULSIs in which devices such as MOSFETs with high density integration are formed on a semiconductor wafer, void defects degrade the transistor gate oxide film. This is reported in the following reference.
Reference 1: Itsumi et al., Journal of Applied Physics, Vol. 78, 1995, pp. 15
A void defect is called a COP (Crystal Originated Particle) or an LSTD (Light Scattering Tomography Defect) according to the wafer evaluation method. As shown in FIG. 1, COPs 3 are void defects which cross the surface of a semiconductor wafer 1. As described in the following reference, these COPs completely disappear when annealing is performed in a high-temperature hydrogen (H.sub.2) atmosphere. As a result, the characteristics of the gate oxide film are greatly improved.
Reference 2: Miyashita et al., Proceeding of for the 24th Ultraclean Technology Symposium, 1995, page 334
Even when annealing is performed, however, LSTDs 2 do not disappear and remain in a surface region about 2 .mu.m deep from the surface on which semiconductor devices are to be formed. These LSTDs lower the insulation resistance or cause defective insulation in element isolation regions, degrading the reverse breakdown voltage characteristic in junctions.
Also, in the generations of ULSI devices having design rules of 0.25 .mu.m or more, e.g., DRAMs (Dynamic Random Access Memories) of 256 Mbits or more, the size of a LSTD can be larger than the design rule for a device. When micropatterning thus advances, the breakdown voltage of the gate oxide film lowers, and various operational of errors occur in the devices which rely on the existence of the LSTDs. The (111) plane of the inner wall of an LSTD is covered with 2- to 3-.mu.m of silicon oxide film. Because of this LSTD has interface state density similar to that of BMD (Bulk Micro Defect) or oxygen precipitates, and function as the center for the generation and recombining of carriers. This may cause a fatal defective leak in DRAMs.
The conventional void defect evaluation is performed as described in Japanese Patent Publication No. 2,520,316. Referring to FIG. 1, silicon on the surface of the semiconductor wafer 1 is dissolved slightly with an ammonia-based cleaning solution (NH.sub.4 OH/H.sub.2 O.sub.2 /H.sub.2 O) to expose the COPs 3 on the surface. A particle counter is used to irradiate the surface with incident light IL1 and detect the COPs 3 by receiving scattered light SL1. This method can detect the COPs 3 on the surface and other defects to a depth of 0.3 .mu.m from the surface. However, the method cannot be used detect the LSTDs 2 at deeper levels 2 .mu.m from the surface.
Although Japanese Patent Publication No. 7-29878 has disclosed a technique for inspecting COPs on the wafer surface, even when a wafer found to be good by this inspection method is used to form devices, internal LSTDs may cause operation errors. However, no conventional methods can reduce LSTDs about 2 .mu.m from the surface of a semiconductor wafer where devices are formed, and thus operational errors still occur.
As described above, no conventional methods can reduce LSTDs in the surface region where devices are formed, although the methods can detect and eliminate COPs on the wafer surface.